fix(plc): 修复RS/SR触发器dst_pin全部为-1的问题
第二遍XML解析时Comb→Gate、Inputs→Gate、R/S属性→Input 链接创建全部未设置dst_pin，导致collect_input_signals 无法区分S/R引脚，SR/RS运算结果错误。 修复内容: - has_comb路径: Comb→链级Gate根据R/S属性匹配Comb#N设置dst_pin - has_comb路径: 链级Inputs→Gate根据R/S属性匹配Input#N设置dst_pin - R/S属性→Input链接改为!ins_el条件下创建，避免与Inputs→Gate重复 - 简单链路径: Inputs→Gate根据R/S属性设置dst_pin
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323dc1ced0
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392fcfb255
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@ -485,6 +485,20 @@ int parse_reclose_logic_xml(const char *file_path, LogicGraph graphs[], int *gra
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if(has_comb)
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if(has_comb)
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{
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{
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// 收集链级 Gate 的 R/S 属性（RS/SR 用）
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const char *gateS = NULL, *gateR = NULL;
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int isChainSRRS = 0;
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if(gate_el)
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{
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int cgtTmp = gate_type_from_xml_str(gate_el->Attribute("type"));
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if(cgtTmp == NODE_TYPE_SR_LATCH || cgtTmp == NODE_TYPE_RS_LATCH)
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{
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isChainSRRS = cgtTmp;
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gateS = gate_el->Attribute("S");
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gateR = gate_el->Attribute("R");
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}
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}
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// 收集所有 Comb 的 Gate 索引（第一遍已解析）
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// 收集所有 Comb 的 Gate 索引（第一遍已解析）
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// Comb Gate → 链级 Gate (一个Comb一根线)
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// Comb Gate → 链级 Gate (一个Comb一根线)
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if(gate_el)
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if(gate_el)
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@ -508,6 +522,18 @@ int parse_reclose_logic_xml(const char *file_path, LogicGraph graphs[], int *gra
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l.src_id = cur->nodes[ci].id;
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l.src_id = cur->nodes[ci].id;
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l.dest_type = cur->nodes[cgi].type;
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l.dest_type = cur->nodes[cgi].type;
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l.dest_id = cur->nodes[cgi].id;
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l.dest_id = cur->nodes[cgi].id;
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// RS/SR: 根据 R/S 属性设置 dst_pin
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if(isChainSRRS)
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{
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int combId = c->IntAttribute("id");
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char combRef[16];
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snprintf(combRef, sizeof(combRef), "Comb#%d", combId);
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if(gateR && strcmp(gateR, combRef) == 0)
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l.dst_pin = (isChainSRRS == NODE_TYPE_SR_LATCH) ? 1 : 0;
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else if(gateS && strcmp(gateS, combRef) == 0)
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l.dst_pin = (isChainSRRS == NODE_TYPE_SR_LATCH) ? 0 : 1;
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}
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}
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}
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}
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}
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}
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}
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@ -535,28 +561,40 @@ int parse_reclose_logic_xml(const char *file_path, LogicGraph graphs[], int *gra
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}
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}
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// 链级 Inputs → 链级 Gate（如 RS/SR 直接连 Input 信号）
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// 链级 Inputs → 链级 Gate（如 RS/SR 直接连 Input 信号）
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if(gate_el && ins_el)
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if(gate_el && ins_el)
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{
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{
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int cgt = gate_type_from_xml_str(gate_el->Attribute("type"));
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int cgt = gate_type_from_xml_str(gate_el->Attribute("type"));
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int cgi = find_node_index(cur, cgt, gate_el->IntAttribute("id"));
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int cgi = find_node_index(cur, cgt, gate_el->IntAttribute("id"));
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if(cgi >= 0)
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if(cgi >= 0)
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{
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{
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for(tinyxml2::XMLElement *sig = ins_el->FirstChildElement("Signal"); sig;
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for(tinyxml2::XMLElement *sig = ins_el->FirstChildElement("Signal"); sig;
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sig = sig->NextSiblingElement("Signal"))
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sig = sig->NextSiblingElement("Signal"))
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{
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{
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if(cur->link_count >= MAX_LINKS_PER_GRAPH) break;
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if(cur->link_count >= MAX_LINKS_PER_GRAPH) break;
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int si = find_node_index(cur, NODE_TYPE_HW_INPUT, sig->IntAttribute("no"));
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int si = find_node_index(cur, NODE_TYPE_HW_INPUT, sig->IntAttribute("no"));
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if(si >= 0)
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if(si >= 0)
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{ LogicLink &l = cur->links[cur->link_count++];
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{ LogicLink &l = cur->links[cur->link_count++];
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memset(&l, 0, sizeof(l)); l.dst_pin = -1;
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memset(&l, 0, sizeof(l)); l.dst_pin = -1;
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l.src_type=NODE_TYPE_HW_INPUT; l.src_id=cur->nodes[si].id;
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l.src_type=NODE_TYPE_HW_INPUT; l.src_id=cur->nodes[si].id;
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l.dest_type=cur->nodes[cgi].type; l.dest_id=cur->nodes[cgi].id; }
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l.dest_type=cur->nodes[cgi].type; l.dest_id=cur->nodes[cgi].id;
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}
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}
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}
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// RS/SR 的 R/S 属性引用的 Input 信号（无 <Inputs> 块时也需创建链接）
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// RS/SR: 根据 R/S 属性设置 dst_pin
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if(gate_el)
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if(isChainSRRS)
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{
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char inRef[16];
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snprintf(inRef, sizeof(inRef), "Input#%d", sig->IntAttribute("no"));
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if(gateR && strcmp(gateR, inRef) == 0)
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l.dst_pin = (isChainSRRS == NODE_TYPE_SR_LATCH) ? 1 : 0;
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else if(gateS && strcmp(gateS, inRef) == 0)
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l.dst_pin = (isChainSRRS == NODE_TYPE_SR_LATCH) ? 0 : 1;
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}
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}
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}
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}
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}
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// RS/SR 的 R/S 属性引用的 Input 信号（仅当无 <Inputs> 块时创建链接，避免重复）
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if(gate_el && !ins_el)
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{
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{
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int cgt = gate_type_from_xml_str(gate_el->Attribute("type"));
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int cgt = gate_type_from_xml_str(gate_el->Attribute("type"));
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if(cgt == NODE_TYPE_SR_LATCH || cgt == NODE_TYPE_RS_LATCH)
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if(cgt == NODE_TYPE_SR_LATCH || cgt == NODE_TYPE_RS_LATCH)
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@ -574,7 +612,8 @@ int parse_reclose_logic_xml(const char *file_path, LogicGraph graphs[], int *gra
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{ LogicLink &l = cur->links[cur->link_count++];
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{ LogicLink &l = cur->links[cur->link_count++];
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memset(&l, 0, sizeof(l)); l.dst_pin = -1;
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memset(&l, 0, sizeof(l)); l.dst_pin = -1;
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l.src_type=NODE_TYPE_HW_INPUT; l.src_id=cur->nodes[si].id;
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l.src_type=NODE_TYPE_HW_INPUT; l.src_id=cur->nodes[si].id;
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l.dest_type=cur->nodes[cgi2].type; l.dest_id=cur->nodes[cgi2].id; }
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l.dest_type=cur->nodes[cgi2].type; l.dest_id=cur->nodes[cgi2].id;
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l.dst_pin = (cgt == NODE_TYPE_SR_LATCH) ? 0 : 1; }
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}
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}
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if(r_attr2 && strncmp(r_attr2, "Input#", 6) == 0)
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if(r_attr2 && strncmp(r_attr2, "Input#", 6) == 0)
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{
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{
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@ -584,7 +623,8 @@ int parse_reclose_logic_xml(const char *file_path, LogicGraph graphs[], int *gra
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{ LogicLink &l = cur->links[cur->link_count++];
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{ LogicLink &l = cur->links[cur->link_count++];
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memset(&l, 0, sizeof(l)); l.dst_pin = -1;
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memset(&l, 0, sizeof(l)); l.dst_pin = -1;
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l.src_type=NODE_TYPE_HW_INPUT; l.src_id=cur->nodes[si].id;
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l.src_type=NODE_TYPE_HW_INPUT; l.src_id=cur->nodes[si].id;
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l.dest_type=cur->nodes[cgi2].type; l.dest_id=cur->nodes[cgi2].id; }
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l.dest_type=cur->nodes[cgi2].type; l.dest_id=cur->nodes[cgi2].id;
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l.dst_pin = (cgt == NODE_TYPE_SR_LATCH) ? 1 : 0; }
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}
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}
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}
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}
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}
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}
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@ -608,7 +648,21 @@ int parse_reclose_logic_xml(const char *file_path, LogicGraph graphs[], int *gra
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{ LogicLink &l = cur->links[cur->link_count++];
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{ LogicLink &l = cur->links[cur->link_count++];
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memset(&l, 0, sizeof(l)); l.dst_pin = -1;
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memset(&l, 0, sizeof(l)); l.dst_pin = -1;
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l.src_type=NODE_TYPE_HW_INPUT; l.src_id=cur->nodes[si].id;
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l.src_type=NODE_TYPE_HW_INPUT; l.src_id=cur->nodes[si].id;
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l.dest_type=cur->nodes[gi].type; l.dest_id=cur->nodes[gi].id; }
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l.dest_type=cur->nodes[gi].type; l.dest_id=cur->nodes[gi].id;
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// SR/RS: 根据 R/S 属性设置 dst_pin
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if(gt == NODE_TYPE_SR_LATCH || gt == NODE_TYPE_RS_LATCH)
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{
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const char *sA = gate_el->Attribute("S");
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const char *rA = gate_el->Attribute("R");
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char inRef[16];
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snprintf(inRef, sizeof(inRef), "Input#%d", sig->IntAttribute("no"));
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if(rA && strcmp(rA, inRef) == 0)
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l.dst_pin = (gt == NODE_TYPE_SR_LATCH) ? 1 : 0;
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else if(sA && strcmp(sA, inRef) == 0)
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l.dst_pin = (gt == NODE_TYPE_SR_LATCH) ? 0 : 1;
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}
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}
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}
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}
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if(ous_el)
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if(ous_el)
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